DESCRIPTION OF THE PRIOR ART
A/D converters, in general, operate according to a particular set of specifications. The most important of these are the resolution (number of bits) and the sampling frequency. For example, an 8 bit, 400 MHz A/D converter has a resolution of 8 bits and can produce 400 Million digital outputs in one second. Flash architecture is one well known method of implementing a high speed A/D converter. An example of flash architecture is disclosed in an article entitled "A 400 MHz input flash converter with error correction", IEEE Journal of Solid State Circuits, Vol. 25, No. 1, pp. 184-191, Feb. 1990 (C. Mangelsdorf). Flash architecture requires 2.sup.N comparators for N bit resolution. Thus, a major drawback of flash architecture is that the size of the converter essentially doubles if the resolution is increased by one bit. As a consequence the power dissipation also roughly doubles, making it almost impractical to use this architecture for more than 10-bits of resolution.
To address the above-mentioned problem attempts have been made to modify basic flash architecture. One such modification is sub-ranging, two-stage, A/D converter architecture as taught by A. G. F. Dingwall and V. Zazzu in "An 8 MHz CMOS Subranging 8-bit A/D Converter", IEEE Journal of Solid State Circuits, Vol. SC-20, No. 6, pp. 1138-1143, 1985. In this architecture, the final A/D converter resolution is obtained by a two step process in which two sequential "passes" are made through a low-resolution flash A/D converter. Although this architecture consumes less space than a standard flash A/D converter (a one-step A/D converter), it suffers from reduced speed since two passes, one after the other, are required to obtain the final conversion. Each of the two stages has the same resolution, and the final A/D output is derived by cascading the outputs of the two stages. For example, if the first stage has 4-bit resolution the second stage will also have 4-bit resolution, with the final word being given by concatenation of the two words in the same order. Conceptually one could use this as a reconfigurable A/D converter by using only the first four bits in certain situations and all eight bits in other situations, but it would be very inefficient because the second pass would still need to be made, even though the information from the pass would be unused.
Many practical variations of this two-stage architecture exist. For example, the operation of the two stages can be pipelined so that the speed of conversion is the same as the conversion time of one stage, and the number of stages can be extended to be more than two. Such multi-step A/D converters are called pipelined multi-step A/D converters, an example of which is shown in an article entitled "A Pipelined 5 MHz Sample/9-bit Analog-to-Digital Converter", IEEE Journal of Solid State Circuits, Vol. SC-22, No. 6, pp. 954-961, Dec. 1987 (Stephen H. Levis and Paul R. Gray). Although the conversion rate is improved in these converters because of the pipelining, there is latency through the A/D converter that is equal to the sum of the delay through all of the stages. Such delay is unacceptable in many applications such as, for example, where the A/D converter is used in a feedback loop (such as in a read channel IC). All of the above-described architectures are attempts to reduce basic problems inherent in flash architecture. However, the concept of reconfigurability of these, and other, types of A/D converters is not addressed by these architectures.
Another well known solution is an interpolating A/D converter as taught by J. Van Valbourg and R. J. Van de Plassche in "An 8b 650 MHz Folding ADC", IEEE Journal of Solid-State Circuits, Vol. SC-27, No. 12, pp. 1662-1666, Dec. 1992. Although this architecture results in a smaller size than a flash A/D converter with comparable speed and resolution, there is no way known to the Applicant herein to reconfigure an interpolating A/D converter to obtain a different resolution (number of bits) or a different speed.
Another solution is the use of a parallel A/D convertor using 2.sup.(n-1) comparators as taught by U.S. Pat. No. 4,928,103. As with prior solutions, while there is a smaller-sized A/D converter produced, there has been heretofore no way known to the Applicant to reconfigure such a convertor to obtain a different resolution or a different speed.
One application in which it would be desirable to be able to switch between a low resolution, high speed A/D convertor and a high resolution, low speed A/D convertor is in a magnetic mass storage device. Magnetic mass storage devices, such as disk drives, are used to store large amounts of data, especially in computer systems. Disk drives include a plurality of magnetized disks and a spindle motor to rotate the disks. Data is stored on concentric data tracks on the surfaces of the magnetized rotating disks. A sensor (usually referred to as a read/write head) positioned proximate the rotating disk and moveable in a radial direction is used to detect (i.e., read) information, in the form of analog signals, from the disks. An important aspect of the operation of the disk drive is the positioning or location of the read/write head with respect to the magnetized tracks on the rotating disk. A servo mechanism is used to determine and control the exact position of the read/write head with respect to the disk, so that data can be read from or written onto a specific sector and track on a specific disk.
Generally, two types of data or information are stored on the disk drive. The first type is user data and this data is read during a user mode. The second type is servo data which is the data used by the servo mechanism to determine the position of the read/write head with respect to a specific sector on a specific track of the disk. The servo data is read in a servo mode.
The electronics that are used for these two read modes vary widely from one manufacturer to another since there are no standards as to how these two processes should be implemented. Typically when reading data in both the user mode and the servo mode, an analog signal detected by the read head is first input into a very low-noise pre-amplifier which amplifies the signal. The amplified signal is then input into a read channel circuit. The read channel circuit is typically a single integrated circuit (IC) which directs the amplified signal to either the read path which processes the user data, or the servo path which processes servo data. In either cases the front end of the read channel, consisting of a voltage gain amplifier (VGA) and a continuous-time filter (CTF), is common to both the servo and read signal processing.
The processing circuitry for the user data is self-contained within the read channel IC (mostly analog). However, only part of the servo processing is done within the read channel IC. The majority of the servo processing, such as DSP operations and voice coil motor driving, is performed by separate circuits using one or more ICs. Essential to the servo processing is an A/D converter for digitizing the analog servo signals. In some disk-drive electronics, this A/D converter is part of the read channel IC, and in others it is embedded in a different chip.
Advances in digital signal processing have led to the need to convert most of the analog signal processing in the user data path into a digital signal processing path. Accordingly, A/D converters are utilized in the user data circuit. However, the servo signal processing, despite sharing most of the analog signal pre-processing with the user data path, continues to use a different A/D converter (either internal or external to the read channel IC) because in processing user data, high speed is more important than high resolution. For servo signal processing high resolution is more important than high speed. The additional circuitry needed to process both types of data results in increased cost for such systems. The current invention pertains to merging these two A/D converters into a single reconfigurable A/D converter with minimal increase in size and cost.